MIPI CSI 2 Tx Rx Silicon Proven Controller IP Cores

MIPI CSI-2 Tx & Rx Controller IP Cores for Highly modular & configurable Camera Interfaces for immediate licensing.
By: contact@t-2-m.com
ORANIENBURG, Germany - April 12, 2022 - PRLog -- T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner's MIPI Alliance Standard MIPI CSI-2 v2.0 Tx and Rx Controller IP Cores for all types of High performance Camera applications. The CSI-2 Tx and Rx IP Cores are Production Proven and have been integrated with matching PHY's in different process nodes in major Fabs.

The MIPI Camera Serial Interface (CSI-2) is an interface between a camera and an image-processing engine. MIPI CSI Transmitter and Receiver adheres to MIPI CSI-2, MIPI D-PHY and MIPI C-PHY specification. The MIPI CSI-2 Transmitter along with MIPI CSI-2 Receiver and MIPI DPHY provides a complete solution for encoding MIPI data. The Layered architecture allows for 4 virtual configurable channels and Colour modes of 16, 18, 24 and 36 bpp. The Controllers can also support YUV420 8, YUV422 8, RGB 888, 565, 666, 555 & 444 and RAW 6, 7, 8, 10, 12 & 14

The MIPI CSI-2 v2.0 Tx Controller IP core is used in mobile and high–speed serial applications where a camera can send the video data using it over MIPI lines to the MIPI CSI Receiver for decoding the data and use it for subsequent processing. It can support up to 3Gbps per trio and 17Gbps in 3 Trios using C-PHY and up to 2.5Gbps per data lane and 10Gbps in 4 Lanes of D-PHY (V2.0). The Controller design also allows for Application Interface in Pixel or AXI interface formats and registering of configuration through CCI interface.

The MIPI CSI-2 v2.0 Rx Controller IP core is used in mobile and high–speed serial applications as a controller for receiving camera video and transmitting camera commands from/to MIPI CSI-2 Transmitter over MIPI lines. Just like the Tx part the CSI-2 Rx IP Core has programmable 1, 2, or 4 Data Lane Configuration. It is able to operate in continuous and non-continuous clock modes due to Active low async reset and clearly demarcated clock domains. It also registers configuration through CCI interface/APB interface.

MIPI CSI-2 Tx and Rx Controller IP Core can also be modified as per customer requirements and provided as a complete solution with MIPI D-PHY IP / MIPI-C PHY IP Cores. Silicon-proven in multiple technology nodes and can be fully integrated and operated with PHYs from multiple PHY vendors. For more information on licensing options and pricing please drop a request / MailTo contact@t-2-m.com

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Tags:MIPI CSI 2 Receiver
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