PCIe 5.0 SerDes PHY & Controller IP Cores For Immediate Licensing!!

MUNICH - March 7, 2022 - PRLog -- T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner's PCI-SIG compliant PCIe 5.0 Serdes PHY IP Cores in 12FFC process nodes with matching PCIe 5.0 Controller IP Core which are silicon proven with High bandwidth and superfast data transfer speed.

The PCIe 5.0 PHY and Controller IP cores supports the PCI 5.0 Specification, compliant with PIPE 5.1. The structured yet simple design allows easy adoption into any design architecture. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. The PHY and Link Layer comes with backward compatibility support for parallel interface: 16/32- bit (Gen5/4), 10/20-bit (Gen3/2/1). The PCIe SerDes PHY and Digital Controller IP Cores provides minimal latency and superfast isochronous data transfer.

The PCIe 5.0 SerDes PHY IP Core in 12nm FFC process technology supports varied data transfer rates of 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s and 32GT/s with four (x4) physical lane width. The 12FFC technology comes with added feature of built-in EYE-monitor and EYE checker, dual-port PLL with LC tanks and a 3-tap FFE for TX preset. Gated power for lowest leakage in L1.2 low power mode, Auto power saving for short reach and Configurable low power mode setting makes the PHY widely applicable for various scenarios under different consideration of power consumption with an Operating Voltage of 0.8V and 1.2V.

The PCIe 5.0 Controller IP Core provides full PCIE Controller functionality with Root Complex and Endpoint BFM modes. It supports queuing for 8 configurable Virtual Channels and multi-function Configurable TC to VC queue mapping. Speed and Link Width negotiation, polarity inversion, and lane-to-lane skew Configurable timers and timeouts allows for high controllability and Scaled Flow Control. Emergency Power Reduction State allows for an advanced power management system.

These IP Cores functionalities are verified in NC-Verilog simulation software using test bench written in Verilog HDL, which are provided with the IP Core delivery.

The PCIe 5.0 SerDes PHY IP core along with the PCIe 5.0 Controller IP core have been used in semiconductor industry's Enterprise computing, storage area networks, Wireless and mobile devices, automotive, IoT, Embedded systems, Graphics devices and other industrial uses…

For more information on licensing options and pricing please drop a request / MailTo: contact@t-2-m.com, please visit: https://t-2-m.com/

Mike Park
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