ASICFPGA releases new ISP core supporting Multiple Pixel Processing of 1,2 or 4 pixels per clock

TORONTO - March 28, 2021 - PRLog -- The ISP cores including HDR, Star and Pro version support Multiple Pixel Processing of 1, 2 or 4 pixels per clock.
The new core could support 4K2Kp60 and 4K2Kp120 at FPGA device.

http://www.asicfpga.com/site_upgrade/asicfpga/isp/isp_core1.html

The camera image signal processing core can be used in security camera, automotive camera, industrial camera and medical camera. Our camera image signal processing core produces high resolution, clear and sharp images by using intelligent and high-performance algorithm. The ISP core uses the minimum logic in spite of using the intelligent and complex algorithm. We can provide the core of the image size, speed, logic size and functions optimized at specific application. The ISP core is provided by Verilog source or FPGA netlist with the document and the testbench for developing FPGA and ASIC.

Features

• Support HDR/Non-HDR image sensor of Sony, On Semicondicutor and Omnvsion, etc.
• HDR processing for two/three Multiple exposure images and HDR bayer image
• Support image sensor of 256*256 ~ 8192*8192 size, including 4K2Kp60 and 4K2Kp120
• Multiple pixel processing of 1, 2 or 4 pixels per clock
• Defect Correction
• Lens Shading Correction
• High quality interpolation
• New Advanced 2D noise reduction and 3D Motion Adaptive noise reduction
• Color correction
• Gamma correction
• WDR (Shadow/Highlight compensation, back light compensation)
• 2D edge enhancement
• support AE, AWB and AF
• Saturation, contrast and brightness control
• Support special images (sepia, negative, solarization)