Digital Down Conversion (DDC) in 5G

INGLEWOOD, Calif. - Jan. 13, 2022 - PRLog -- The DDC module is made up of a carrier selector, frequency down converter, filer, and decimator that all work together to provide a real signal. In addition to interpolation, filtering, a frequency upconverter, and a carrier combiner, a typical DUC module produces a complex signal at DC. Lower interface data rates are advised to save power, money, and high-speed logic in FPGAs/ASICs.

The combination of NCO and mixer reduces the complexity of the filter and decimator stages, suppressing unwanted signals using a low pass filter and decimator for a factor of two lower data rates. Decimation will be more than 2 for increased flexibility with RF ADCs.

Configures the GSM Digital Down Converter in MATLAB with a sample rate of 69.333 MSPS and a decimation factor of 256 to achieve an output sample rate of 270.83 kHz, with the DDC object automatically factoring the decimation value so that the CIC filter decimates by 64, the CIC compensator decimates by 2, and the third stage filter decimates by 2.

The DDC object generates decimation filters automatically based on a set of passband and stopband attenuation and frequency criteria.

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