Axiom Announces New Technologies to Address Verification Challenges

UVM Debugger, Coverage Closure and Unlimited Site License Address Key Customer Concerns
May 30, 2012 - PRLog -- Milpitas, California, May 30, 2012 --Axiom Design Automation, provider of fastest path to verification closure for semiconductor design, today announced that it has added several new capabilities to its flagship MPSim product to address key concerns as design complexity continues to increase and customers migrate to SystemVerliog and UVM methodologies. These new capabilities will be showcased at DAC in San Francisco, June 4 -6, in Axiom Booth #1625.

During the past year, Axiom has been working very closely with its customers in helping them migrate to SystemVerilog and UVM methodology. During the transition, three areas were clearly seen as posing major challenge.

●   The new UVM industry standard required new debugging capabilities, which did not exist in any integrated debuggers.
●   Getting to 95% coverage closure remains a major challenge and was consuming lot of simulation cycles.
●   Complexity of new chips coupled with the coverage challenge, required literally thousands of simulation licenses to complete the several thousand test cases in the regression suite in reasonable time.

“We focused on these issues and introduced several new capabilities that are specifically targeted at UVM debugging and coverage closure”, said Badru Agrawala, President and CEO, Axiom Design Automation. “Our focus on technology is paying off, as we saw over 50% growth in our business in the past year, with many new customers adopting MPSim. Our best-in-class RTL debugging capabilities combined with our newly released UVM debugging is helping our customers debug their UVM designs much faster”.

“Our company is focused on providing advanced verification training and services”, stated Srinivasan Venkataramana, CTO of  CVC, Bangalore, India. “We are seeing a clear shift to SystemVerilog and UVM methodology for verification. Most of our customers struggle to get productive with UVM due to the difficulty in debugging these environments. In our experience, the existing verification solutions are lacking the capability for effective debugging of UVM. Axiom’s MPSim is the only simulator on the market today that effectively addresses the debugging challenges of SystemVerilog and UVM. Some of the advanced capabilities of DesignerUVM such as topology visualization, objection debug, extracting transactions from log file are truly trail blazing and will significantly enhance users’ verification productivity”.
“You can run lots of simulations, but ultimately the engineering productivity comes from the ability to debug designs and testbench”, said Gary Smith, Chief Analyst of Gary Smith EDA.  “With rapid adoption of UVM, integrated debug will be a critical technology that will differentiate simulator vendors”.

Some of the advanced capabilities recently added to MPSim include:

●   DesignerUVM –  Most Comprehensive Debugging Environment for UVM
Latest innovations in UVM debug include - UVM Component Hierarchy based debug, Context Sensitive Debug, Automated Message Extraction, Transaction based debug (including transaction viewing in waveforms), UVM Port and sequence connectivity schematic, Virtual Interface tracking, Objections tracking, Global resource and configuration database visualization and more.

●   Coverage --  Most advanced Coverage Tool Using Formal Analysis
Axiom has developed unique technology that includes root cause identification, coverage equivalence and advance filtering.

●   WUL  -- Worldwide Unlimited Licensing
Unlimited site license at fixed affordable cost.

These capabilities will be demonstrated at DAC at Axiom Booth  #1625.
About Axiom
Axiom Design Automation is a company focused on providing the best-in-class verification platform to address the growing complexity of today’s FPGAs, ICs, SOCs and systems. Axiom’s flagship product, MPSim is the state-of-the-art, industry proven high performance SystemVerilog simulator integrated with an advanced debugger, compiled testbench automation, multiple clock domain verification and comprehensive coverage analysis for quick verification closure. MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in single kernel architecture for maximum performance. MPSim is fully compliant with industry standards such as VMM, OVM, UVM, UPF, etc. For more information please visit

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