Altera FPGA based SATA Host Controller Design
iWave systems developed SATA Host Controller design targeted for integration with Altera’s Cyclone V SoC series FPGA devices to provide an industry-compliant SATA 1.5-Gbps and SATA 3.0-Gbps interface.
The above block diagram shows the internal blocks of the SATA host controller IP. The SATA host controller include Link and Physical (PHY) Layer. The Link layer is responsible for taking data from the constructed frames, encoding or decoding each byte using 8b/10b, and inserting primitives (e.g. ALIGNp, SYNCp). The Physical layer is responsible for transmitting and receiving the encoded information as a serial data stream on the SATA interface. SATA protocol supports the out-of-band (OOB) signaling scheme. Out-of-band signaling is used for the following functions:
· Establish communication between a host and drive to identify the type of drive used in the system
· Identify the maximum operating data rate of the host and drive
An out-of-band signal is a tri-level signal that contains a pattern of idle and burst signals. Out-of-band signaling is used to identify the specific actions during conditions; such as receiving interface is inactive or in low power state mode. The out-of-band signals comprise of COMRESET, COMINIT/COMWAKE. Altera devices are designed/configured to operate with GXB Transceiver (Gigabit Transceiver Block) on Cyclone V SoC to generate and detect out-of-band sequences through the transmitter electrical idle and receiver signal detect features.
iWave has developed Hardware and Software solutions around the Altera's Cyclone V SX Series SoC based System On Module (SOM). The SOM is also compatible with latest Qseven specification version R2.0 supporting all the major high speed interfaces like SATA, Gigabit Ethernet, LVDS, multiple USB 2.0 host ports and many more.
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