Calypto Launches Webinar Series on High Level Synthesis and RTL Power Optimization

Calypto Launches its Webinar Series on High Level Synthesis and RTL Power Optimization
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Calypto Design Systems


San Jose - California - US


Nov. 29, 2012 - PRLog -- SAN JOSE, Calif., – November 29, 2012 – Calypto® Design Systems (, Inc., the leader in electronic system level[TGB1] (#_msocom_1)  (ESL) hardware design and register transfer level (RTL) power optimization, today announced it is launching a series of monthly webinars aimed at educating the design community on the latest in high level synthesis (HLS) and power optimization techniques for RTL-based designs.

The first two webinars are “Minimizing RTL Power through Sequential Analysis”, held Tuesday, December 4 at 11:00 AM PST, and “A Practical Comparison Between C++ and SystemC for High Level Synthesis”, on Thursday, December 13 at 11:00 AM PST. Due to the timeliness of the topics and the “true” technical tutorial content of the webinars, signups have been brisk with the current registration for each webinar nearing the maximum capacity of 150.

To attend these webinars, sign up at

To receive announcements of future webinars, sign up for our E-Newsletter at

About Calypto Products

Calypto’s Catapult® High Level Synthesis, SLEC (® (Sequential Logic Equivalence Checking), and PowerPro® platforms are used by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable electronic system level design to dramatically improve design quality and reduce power consumption of their system-on-chip (SoC) devices.

About Calypto

Calypto Design Systems Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, and Si2, and it is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan, and North America. More information can be found at

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Press Contact:

Linda Marchant, Cayenne Communications for Calypto, 919-451-0776,


AMBA:      Advanced Microcontroller Bus Architecture

AXI:          Advanced eXtensible Interface

ESL:          Electronic System Level

HLS:          High Level Synthesis

RTL:          Register Transfer Level

SoC:          System on Chip

TLM:         Transaction Level Modeling

Catapult, Calypto, PowerPro, and SLEC are trademarks of Calypto Design Systems Inc.

All other trademarks are the property of their respective owners.

Search Terms

High-level synthesis




Power optimization

Power reduction

RTL power optimization

[TGB1] (http://#_msoanchor_1)made this spell out and those for RTL and HLS low case to match usage in paragraph 4 and because it is more standard treatment.
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Tags:Catapult, Calypto Design Systems, SLEC, PowerPro, Webinar
Location:San Jose - California - United States
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