Microsis releases FBIP 1553FT

Sept. 3, 2009 - PRLog -- Ⅰ.INTRODUCTION
Zhuhai Microsis’ 1553B controller IP core” FBIP1553FT” is fully compliant with MIL-STD-1553A/B standard, and supports all the types of MIL-STD-1553A/B messages. All the three types of MIL-STD-1553A/B devices are implemented in “FBIP1553FT”, which could be configured as BC, MT or RT by software. It can also be configured as single function device, such as single BC, MT or single RT.

Regarding the High Reliability Bus requirement of Military, Aviation and Aerospace area, the fault tolerant design and fail safe design scheme are used in the IP core design. Registers and built-in memory units are all designed with Fault tolerant design scheme, which can automatically correct Single memory/register bit error induced by Single Event Upset (SEU), which is caused by hard environment conditions, such as radiation, Electromagnetic Interference, etc.

Ⅱ.FEATURES
2.1. Conforms to MIL-STD-1553A/B Standard, and supports all the messages  format defined by MIL-STD-1553A/B standard:
2.1.1. BC → RT;
2.1.2. RT → BC;
2.1.3. RT → RT;
2.1.4. Broadcast;
2.1.5. Mode code;
2.2. Bus Controller(BC):
2.2.1.Supports automatic retry;
2.2.2.Configurable retry policy:
2.2.2.1.Configurable retry times.
2.2.2.2.Channel alternation configurable.
2.3. Message frame automatically repeat:
2.3.1. Programmable message gap and frame gap.
2.3.2. Programmable response timeout.
2.4. Remote terminal(RT):
2.4.1. Supports various of memory management:
2.4.1.1. Support Single buffer.
2.4.1.2. Support Double buffer.
2.4.1.3. Support Circular buffer.
2.4.2. Configurable illegal command look up table:
The incoming command could be illegalized, according to the direction, sub-address and word count field. If illegalized, the ME bit of the status word would be set.
2.4.3. configurable selective mode code interrupt table Interruption could be generated with each mode command received.
2.5. configurable busy bit lookup table:
2.5.1. The busy bit of the status word could be set/clear according to individual sub-address configuration.
2.5.2. The controller enters default RT Mode after power up, with global “busy” bit set, all the incoming command would be replied with “busy” (busy bit set in status word).
2.6. Bus monitor(BM):
2.6.1. Bus word oriented monitor.
2.6.2. Programmable trigger word.
2.6.3. Bus word identification word would be saved in pare with the received bus word, to prov-ide additional information for the software, such as which channel the bus word was rec-eived, the inter-word gap vale, etc.
2.7. MISC:
2.7.1. FBIP1553FT was coded with VHDL at RTL level, which is fully synthesizable. The IP core is technology independent; it could be implemented in FPGA and as ASIC;
2.7.2. Register operation and memory layout is compatible with DDC BU6158X;
2.7.3. Configurable built-in memory, which could be configured up to 64K word(Double byte);
2.7.4. Asynchronous Bus interface,Support both 8-bit and 16-bit host interface;
2.7.5. To meet the requirements of Military, Aviation and Aerospace applications, the IP core is Designed with fault tolerant scheme, which can resist Single Event Upset (SEU);
2.7.6. Fail-safe design methodology is applied in the IP core design. When the environment condition beyond the fault tolerant capability of the controller, it will return to idle state, to avoid malfunction;
2.7.7. Supports Nowadays Popular MIL-STD-1553B Bus transceiver.

Ⅲ.IP CORE EVALUATION KIT
FBIP1553FT IP Core Evaluation Kit includes an  evaluation board, a demo program sourcecode coded with ANSI C, and a portfilo of technique document. The evaluation board was designed with MCS-51 and ALTERA’s CYCLONE FPGA, the demo program is compiled withKEIL C. A build-in monitor is implemented in the demo program, users could monitor the programstate VIA an RS232 cable, using the “Super Terminal” software provided with MicroSoft’s Windows OS.

Ⅳ.SUPPORTED EPGA DEVICES
4.1. ALTERA CYLONEI/II/III and STRATIX
4.2. XILINX SPARTAN and VIRTEX
4.3. ACTEL PROASIC

Available
4.4. FPGA net list
4.5. ASIC net list
4.6. RTL source code

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Zhuhai Mircosis Electronic Technology Co., Ltd focuses on developing test/measurement products and high-reliability system.
Base on “ANYTEST" platform technology, we've developed series of test/measure instruments/equipments. AT15XXX series products is a package of MIL-STD-1553A/B bus test solution. Since brought to market, it's been welcomed by users for its detailed and user-friendly design. With the help of AT15XXX, the 1553B bus products test is no longer complicate.
Base on our long-term technique deposition of high-reliability IP cores, including peripheral IP cores, bus controller IP cores and microprocessor IP cores, we would provide customers a package of high-reliability embedded computer solutions. Such a solution could be implemented in an FPGA or in an ASIC chip. With this solution, he volume of the computer would be minimized greatly, and the reliability would be improved highly.