Introduction to the New Overshoot and Undershoot Tests for 1.6T Optical Modules

SHENZHEN, China - July 24, 2026 - PRLog -- I. Why Does 1.6T Require New Dedicated Tests?

For previous-generation 400G and 800G optical modules, signal quality could be adequately evaluated using Eye Diagram masks and TDECQ measurements alone, without dedicated Overshoot or Undershoot testing.

The reason is straightforward: lower-speed electrical signals transition more gradually, making transient waveform abnormalities extremely rare and having little impact on system performance.

The transition to 1.6T transmission fundamentally changes this situation.

According to the IEEE 802.3dj specification, 1.6T optical modules employ 112 Gbaud PAM4 modulation, delivering 224 Gb/s per lane. Eight electrical lanes are aggregated to achieve an overall bandwidth of 1.6 Tb/s, with a Unit Interval (UI) of only 8.92 ps.

Such an extremely narrow timing window and ultra-fast signal transitions mean that even slight hardware imperfections or parameter deviations can cause waveform distortion.

Traditional testing methods mainly evaluate steady-state signal quality and therefore have several limitations:

• Limited measurement scope: Only steady-state signal characteristics at sampling points are measured, making transient waveform distortions invisible.
• Incomplete risk coverage: Overall signal degradation is evaluated, while transient voltage spikes that may damage chips or optical components are overlooked.
• Insufficient stress evaluation: Signal degradation under extreme operating conditions, such as high/low temperatures or heavy workloads, may remain undetected.
• Limited long-term reliability assessment: Existing tests identify immediate bit errors but provide little insight into long-term aging and reliability.

II. Understanding Overshoot and Undershoot
Overshoot & undershoot are common transient voltage distortions on 1.6T transceivers, triggered by PCB impedance breaks, poor connectors, over-compensation and high-frequency interference.

Now required by IEEE 802.3dj, this dynamic test complements eye diagram & TDECQ: it catches hidden waveform glitches, avoids chip damage, reduces bit errors, and exposes latent reliability risks before mass production.

Industry baseline limit: 22%; leading cloud operators adopt stricter 10%–15% thresholds.

This new test standard strengthens full signal integrity validation, laying a solid hardware foundation for reliable AI hyperscale interconnection.
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