Axiom Enhances SystemVerilog Verification with OVM and VMM

May 11, 2010 - PRLog -- Milpitas, California, May 11, 2010, --Axiom Design Automation, provider of fastest path to verification closure for semiconductor design today announced the release of version 5.0 of MPSim, industry’s price/performance leading SystemVerilog verification platform. Version 5.0 of MPSim offers significant new capabilities in simulation performance, debugging, coverage analysis and SystemVerilog enhancements including complete support for both VMM 1.2 and OVM 2.1. New in MPSim 5.0 is a unique SVA engine that enables on-the-fly what-if analysis without requiring the user to re-run simulation. Combined with multi-core support, compiled testbench including SystemVerilog and OpenVera, comprehensive coverage closure technology and best-in-class integrated graphical debugger, MPSim offers the most complete verification solution in a single unified kernel architecture for maximum performance.

"We successfully taped out our last chip that was verified using Axiom’s MPSim simulator”,  stated Fen-Yu Su, Principal Engineer, Bay Microsystems. “We are very impressed with MPSim’s performance. We have seen excellent performance while dumping waveforms and interactive debugging. The Designer debugger is one of the best I have seen in the industry."

Release 5.0 also includes many improvements in the area of Coverage closure. These include FSM coverage, SVA coverage, sophisticated coverage merge and filtering capabilities and coverage based test grading. FSM coverage includes coverage information related to FSM states and FSM transitions between states, showing results for each state and each closed transitional path in the state machine. Coverage based test grading is a powerful new feature that allows the users to grade simulation diags based on their code and functional coverage results.

“At Axiom we are committed to providing the best verification solution to our customers”, said Badru Agarwala, President and CEO of Axiom Design Automation. “We continue to invest in technology to bring the latest innovations in the tool. Because of our technological leadership, MPSim is seeing wider adoption in the industry and many customers have successfully taped out several complex chips exclusively using MPSim for functional verification.”

“We have taped out several chips using MPSim for RTL to 64 bit gate level simulation with full SDF back annotated timing and testbenches”, stated Krist Roginski,  CAD Manager  at Cortina Systems.  “MPSim clearly provides the most comprehensive and best price/performance verification solution in a single package and we are very happy with the tool.”

About Axiom
Axiom-DA is a company focused on providing the best-in-class verification platform to address the growing complexity of today’s FPGAs, ICs, SOCs and systems. Axiom’s flagship product, MPSim is the state-of-the-art, industry proven high performance SystemVerilog simulator integrated with an advanced debugger, compiled testbench automation, multiple clock domain verification and comprehensive coverage analysis for quick verification closure. MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in a single kernel architecture for maximum performance.


For more information, contact:
Ghulam Nurie
gnurie@axiom-da.com

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About Axiom
Axiom-DA is a company focused on providing the best-in-class verification platform to address the growing complexity of today’s FPGAs, ICs, SOCs and systems. Axiom’s flagship product, MPSim is the state-of-the-art, industry proven high performance SystemVerilog simulator integrated with an advanced debugger, compiled testbench automation, multiple clock domain verification and comprehensive coverage analysis for quick verification closure. MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in a single kernel architecture for maximum performance.