US P/N 7,376,014 covers a nonvolatile memory whose reliability and endurance have been improved by reducing the impact of disturbs and also ensuring isolation from neighboring cells.
US P/N 7,583,530 covers structures for storing more than one bit in a cell – at differing locations using a non-spreading storage medium.
US P/N 7,149,125 and 7,227,786 cover location specific storage cell structures and operation, including low voltage programming and erase methods.
US P/N 7,224,620 and 7,193,900 cover programming and erase capability based on the CACT and TG Program erase methods for programming and erasing of a non-volatile memory cell.
US P/N 5,506,431 and 5,519,653 cover low voltage programming where the acceleration of carriers is used to reduce the voltage needed to overcome the potential barrier.
US P/N 5,790,455; 5,986,931; 6,201,732; 6,574,140; 110307 (Taiwan); and
64015 (Singapore), are applicable to embedded and medium size NVM arrays with very high retention and read-write cycling capability.
US P/N 6,451,652 minimizes the masks used for self-alignment during manufacturing.
US P/N 6,411,545 covers a non-volatile latch for high reliability embedded applications.
US P/N 6,534,816; 6,479,863; and 6,384,451 cover various tunneling charge injector functionalities for floating gate memory cells.
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