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OmniPhy Announces 2.5v I/O Transistor based Mixed Signal PHY Availability in TSMC 28nm HPM

28nm Product line includes Gigabit Ethernet PHY, DDR4/3, HDMI 2.0, and SerDes

 
PRLog - May 21, 2014 - SAN JOSE, Calif. -- San Jose, California, May 22, 2014 – OmniPhy a provider of differentiated Analog & Mixed Signal Interface IP, announced the availability of its Interface PHY product line on Taiwan Semiconductor Manufacturing (TSMC) 28nm HPM process, designed using 2.5v I/O transistors.

These highly-integrated Interface PHY’s lead the industry in jitter performance, small package size and low power consumption.

The OmniPhy Mixed-Signal Intellectual Property includes,

·        Giga Bit Ethernet PHY

·        USB 3.0 / 2.0 PHY

·        PCI Express 3.0 / 2.0 PHY

·        SerDes PHY

·        DDR4/3 PHY

·        HDMI 2.0 PHY

all of which are available both in both 2.5v I/O transistor and 1.8v I/O transistor design.

“The challenge of identifying market opportunities for new product development, and successfully leveraging resources to capitalize on these opportunities is a critical element in the success of OmniPhy,” said Ritesh Saraf, OmniPhy’s Chief Operating Officer.

“Our 2.5v I/O transistor based PHY products allows designers to choose the best configurations to optimize power, performance and area for their applications SOC’s.”

The salient features our 2.5v I/O device based PHY library are,

·        Higher Reliability

·        Stronger ESD Performance

·        High Yield on 28nm process

·        Less Leakage Power

·        Easier and more cost effective to port legacy SOC designs


A key advantage of the 2.5v I/O device based PHY IP is that no high voltage generation circuitry is required – all programming and re-programming is done using a standard CMOS technology with no additional masks or process adaption. This allows designs to operate from a single I/O supply, eliminating the complication of generating a separate, high-voltage signal to support legacy interface standards, or supporting a high-voltage I/O pad.

“Our customers provide a point of balance in the development of new products, simultaneously validating market and design decisions, while empowering the satisfaction of their unique needs – thus differentiating our products from our competitors,” said Claude Gauthier, Chief Operating Officer at OmniPhy.

“The decision not to support the 2.5v I/O transistor based design at 28nm by the EDA vendors forced SOC designers to adopt an expensive path of porting all their legacy interfaces to 1.8v I/O. We saw a unique opportunity to service the SOC market at 28nm with our 2.5v I/O transistor based PHY designs.

This most basic, but surprisingly elusive, information was essential to the success of our product and service offering”.

Availability

The 2.5v I/O transistor PHY Library is available now for 28 nanometer (nm) HPM process technology. OmniPhy’s Interface IP portfolio for System on Chip (SOC) includes solutions for  10/100/1G Ethernet, DDR4/3, PCI Express 3.0/2.0, USB 3.0/2.0, SATA and HDMI 2.0, all of which are available now.

About OmniPhy

OmniPhy is a leading provider of high-quality, silicon-proven IP solutions for system-on-chip (SoC) Interface designs. The broad IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP and subsystems. With a robust IP development methodology, extensive investment in quality, IP prototyping and comprehensive technical support, OmniPhy enables designers to accelerate time-to-market and reduce integration risk. For more information on OmniPhy IP, visit http://omniphysemi.com.

Contact
Senthil Nathan
***@omniphysemi.com

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Source:OmniPhy Semiconductor
Location:San Jose - California - United States
Industry:Engineering, Semiconductors
Tags:TSMC, cadence, synopsys, interface, phy
Shortcut:prlog.org/12326375
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