The first two webinars are “Minimizing RTL Power through Sequential Analysis”, held Tuesday, December 4 at 11:00 AM PST, and “A Practical Comparison Between C++ and SystemC for High Level Synthesis”, on Thursday, December 13 at 11:00 AM PST. Due to the timeliness of the topics and the “true” technical tutorial content of the webinars, signups have been brisk with the current registration for each webinar nearing the maximum capacity of 150.
To attend these webinars, sign up at www.calypto.com/
To receive announcements of future webinars, sign up for our E-Newsletter at www.calypto.com.
About Calypto Products
Calypto’s Catapult® High Level Synthesis, SLEC (http://www.calypto.com/
Calypto Design Systems Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, and Si2, and it is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan, and North America. More information can be found at www.calypto.com.
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Linda Marchant, Cayenne Communications for Calypto, 919-451-0776, linda.marchant@
AMBA: Advanced Microcontroller Bus Architecture
AXI: Advanced eXtensible Interface
ESL: Electronic System Level
HLS: High Level Synthesis
RTL: Register Transfer Level
SoC: System on Chip
TLM: Transaction Level Modeling
Catapult, Calypto, PowerPro, and SLEC are trademarks of Calypto Design Systems Inc.
All other trademarks are the property of their respective owners.
RTL power optimization