“After enabling several successful tapeouts for customers using our simulator with native OVM technology support, we have continued to enhance our SystemVerilog capability”, stated Tarak Parikh, Vice President of Products at Axiom Design Automation. “Axiom’s UVM implementation supports UVM libraries and methodologies without requiring any changes to the libraries. UVM clearly provides a huge verification productivity boost to our customers. However, our experience with our beta UVM customers highlighted the complexities involved in debugging testbenches created with UVM and we responded accordingly. Axiom today provides the best in class debug technology for integrated verification debugging and our customers testify to its unique debug capabilities in the areas of design and testbench as one of the key reasons for their ability to verify their designs on time. Our growing list of successful customers validates our strategic focus on continued innovation in the product taking advantage of the latest hardware and software technologies”
MPSim is a complete Verilog/SystemVerilog verification platform with full support for SystemVerilog, OVM, VMM, and UVM. It includes an advanced debugger in a single architecture resulting in high performance and throughput. MPSim also includes comprehensive coverage analysis that covers both functional and structural coverage. MPSim offers the most complete verification solution in a single unified kernel architecture for maximum performance. MPSim is production proven with several very large and complex chips taped out.
Axiom Design Automation is a company focused on providing the best-in-class verification platform to address the growing complexity of today’s FPGAs, ICs, SOCs and systems. Axiom’s flagship product, MPSim is the state-of-the-
For more information, contact:
Ghulam Nurie at gnurie@axiom-
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Axiom’s provides industry proven high performance SystemVerilog simulator integrated with advanced debugger, compiled testbench automation, multiple clock domain verification and comprehensive coverage analysis for quick verification closure.