3D-IC TSV Interconnects:
Market Trends
The continuation of Moore’s law by conventional CMOS scaling is becoming more and more challenging, requiring huge capital investments. 3D Packaging with 3D TSV interconnects provides another path towards the “More than Moore”, with relatively smaller capital investments. Despite the impact of the economic downturn, 3D integration investments are strategic innovations and have continued. ( http://www.bharatbook.com/
We have identified as of today more than 15 different 300mm 3-D IC pilot lines running or being installed world-wide (within R&D centers, at packaging houses, CMOS foundries or within IDM fabs).
This year, several initiatives of key industry leaders happened such as STMicro for 3D integration in MEMS and CMOS image sensors, Elpida for stacked DRAM memories and Sony with the introduction of Backside illuminated (BSI) technology into its camera sensor products portfolio.
Strong dynamics in MEMS, CMOS image sensors, memory, analog and logic industries continue and will drive adoption of 3D TSVs to high volumes within the next decade. Additionally, new applications such as HB-LED silicon modules, Solar and Power components are also on the point to catch the 3D TSV trend and to benefit from this disruptive interconnect technology!
Key features of the Reports
• Updated market forecasts & technology roadmaps for 3D IC components:
– Impact of the economic downturn on the 3D TSV market
– Market forecast update for MEMS, CMOS image sensors, logic, analog and memory applications
– New application areas covered: HB-LED modules, power and solar components
– Business case for 3D interposers:
• 3D IC players 2008 market shares & revenues breakdown in $M (as packaging services or estimated in relative packaging value)
• Supply chain perspectives, key players and emerging infrastructure for 3D Packaging
• Strategic technology choices for 3D integration scenarios:
– Analysis of the different possibility for the implementation of TSVs and the rationale behind (via first / via middle / via last / via after bonding)
– Analysis of the cost structure for different implementation cases (vias in front-end, vias at packaging assembly house, C2W versus W2W, …)
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