PK Outside The Box
The evaluation of system design options for RSA implementations on an embedded RISC processor or a dedicated RSA Silicon IP offload processor requires modular mathematics number theory that most engineers may have learned and forgotten years ago. Now that they may have to consider an RSA cryptographic application for their System On Chip design, a concise treatment of the theory is quite likely to be well-appreciated.
To this end, Crack Semiconductor (http://www.cracksemi.com) has published a White Paper entitled "Theory and Best Practice in RSA Offload Processor Design". The paper may be seen as an important summary of the underlying number theory applied to RSA cryptography and the Diffie-Hellman Key Exchange.
The White Paper can be read at http://cracksemi.com/
The basic modular arithmetic concepts are introduced and then these are applied to the problems of modular multiplication and exponentiation on “big integers” in the order of a thousand or more bits.
Nearing the end of the paper, the RSA modexp computations are shown to take a lot of time on an embedded RISC processor, so that one might want to “offload” the job to a specially designed RSA processor.
At the end of the paper, even though special purpose RSA offload processors exist on the Silicon IP market, there is still room and the need for innovation. So we introduce the CS1024-RSA offload processor, delivering 177 RSA 1024-bit decryptions per second at 200 Mhz using a 32-bit multiplier, as what is expected in a “best practice” in RSA offload processor design
Photo:
http://www.prlog.org/
