Crack Semiconductor Publishes PKA Silicon IP White Paper

PR Log (Press Release) – Aug 31, 2009 – Crack Semiconductor begins its new White Paper with a review of basic RSA and ECC public key algorithms and computation models. The paper alludes to subtleties of the underlying modular mathematics and discusses a number of best practices for implementation of a dual-algorithm PKA processor for RSA and ECC applications as Silicon IP.

The White Paper explains how differences in RSA and ECC appear to "box in" an efficient solution for both algorithms. The paper then proceeds to take PK “outside the box” by explaining how the development of its PKA processor architecture called SIMPLR(TM) is founded on important new insights into the modular math functions applied to Silicon IP.  While RSA and ECC present different and potentially constraining problems for the PKA designer, Crack Semiconductor's new SIMPLR(TM) PKA processor integrates these apparent area-busting constraints into an opportunity for advancing the state-of-the-art. At the bottom line, this translates into significantly improved compute offload in terms of PKA performance versus Silicon gate area and consumed power.  Because the design is parametric, these capabilities enable the best mix of performance versus area for most applications, typically reduced to choice of ALU (data path) width.

The White Paper is access-controlled on the company's website, so interested readers are requested to contact art@cracksemi.com for express permission to access the paper.