nSys Demonstrates Verification IP for PCIe 3.0 at the PCISIG DevCon 09

Newark - nSys Design Systems will demonstrate Verification IP for PCIe® 3.0, which is currently at preliminary revision 0.5
By: Prachi Khaneja, nSys Design Systems
 
July 15, 2009 - PRLog -- Newark - nSys Design Systems will demonstrate Verification IP for PCIe® 3.0, which is currently at preliminary revision 0.5, at the PCI-SIG® DevCon 2009, to be held in Santa Clara, CA on July 15-16, 2009.

“In our endeavor to take PCI to the next generation, we have consistently relied upon PCI-SIG member companies including nSys as part of the PCIe ecosystem,” said Al Yanes, chairman and president, PCI-SIG. “nSys has been actively sponsoring PCI-SIG developers conferences around the world for more than five years now and we appreciate their willingness to  share their experiences and expertise by presenting papers that benefit other members.”

“nSys has a comprehensive Verification IP for PCIe 2.0/ 1.0, in native Verilog and SystemVerilog,” said Atul Bhatia, CEO, nSys Design Systems. “As PCIe 3.0 is still evolving, it is our endeavor as an observer of the protocol working group, to make available the interim solutions for Verification IP to industry leaders.”

About nSys: nSys leverages the world’s largest portfolio of Verification IPs it has developed, to provide products & services to Accelerate Designs for its customers developing ASIC, FPGA or IP. The nVS family has proven Verification IPs in SystemVerilog and Verilog for standard interfaces/protocols such as PCI Express, SATA 3.0, SAS, AXI, AHB, APB, USB 2.0, SuperSpeed USB 3.0, DDR2, DDR3, Ethernet etc. For more information, please visit nSys online at www.nsysinc.com

About PCI-SIG: The PCI Special Interest Group (PCI-SIG) actively promotes PCI technology through a series of events. Members can test products at compliance workshops, receive PCI training at technical update seminars, participate in industry education and aid in promoting PCI technology at select tradeshows. For further information visit www.pcisig.com

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nSys leverages the world’s largest portfolio of Verification IPs it has developed, to provide products & services to Accelerate Designs of its customers developing ASIC, FPGA or IP. nSys is committed to quality processes and is well conversed with ISO and SEI-CMM guidelines.
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Source:Prachi Khaneja, nSys Design Systems
Email:***@nsysinc.com Email Verified
Tags:Verification Ip, Usb 3 0, Ethernet, Pci Express, Pci Gen3, Nsys, Superspeed Usb, Verification
Industry:Engineering, Semiconductors, Services
Location:United States
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