Citing Steve Casselman, DRC CTO and generally recognized as the “Father of Reconfigurable Computing”, the article details how CPU vendors acknowledged that Moore’s Law could no longer deliver enough computing power to satisfy time-critical, data-intense applications like high volume, web based applications and services. AMD was the first to respond opening their HyperTransport bus to coprocessors.
This was the last barrier to coprocessors moving from a specialized niche product to mainstream computing. The DRC coprocessor executes applications at hardware speeds and can therefore achieve accelerations of up to 100 times that of standard commodity CPUs.
The DRC architecture is optimized for applications that require ultra-fast search, sort or encrypt. By deploying a massively parallel on chip architecture applications can execute tens of threads simultaneously.
The full article can be found on the FPGA Journal website at:
http://www.fpgajournal.com/
